With the development of integrated circuit (IC) technology, the integration degree of semiconductor devices has been consistently increasing, and the size of the semiconductor devices has become smaller and smaller. In order to lower the parasitic capacitances of the gate of MOS transistors and increase the device speed, high-K metal gate (HKMG) structures have been introduced in the MOS transistors. Conductive vias may often be used in the MOS transistors to form electrical interconnection structures. The conductive vias may usually be formed in source regions, drain regions and/or the surfaces of the HKMG structures. However, the size of the conductive vias may be difficult to further decrease because of process limitations, which may limit further size decreasing of the source regions, the drain regions, and the HKMG structures. Therefore, the integration degree of semiconductor devices may be unable to continuously increase.
In order to increase the integration degree, a shared via structure, i.e., the drain region and the HKMG structure share a same conductive via, has been developed. The shared via structure may reduce the size of the drain region and the HKMG structure.
FIGS. 1˜5 show semiconductor structures corresponding to certain stages of an existing fabrication process for forming an MOS transistor with a shared conductive via structure.
As shown in FIG. 1, a semiconductor substrate 10 is provided, and an HKMG structure 20 sequentially having a gate dielectric layer 21, a metal gate 22, and a sidewall 23 is formed on the semiconductor substrate 10. Further, a source region 30 and a drain region 40 are formed in the semiconductor substrate 10 at both sides of the HKMG structure 20. Further, a contact-hole-etch-stop layer 50 may be formed on the surface of the source region 30, the surface of the drain region 40 and the surface of the HKMG structure 20. Further, an interlayer dielectric layer 60 may be formed on the contact-hole-etch stop layer 50.
When the metal gate 22 is formed, because the metal may unlikely to avoid oxygen in the air, a metal oxide layer may be formed on the top of the metal gate 22 (not shown). The metal oxide layer may need to be removed before subsequently forming a conductive via.
Further, as shown in FIG. 2, a first contact hole 70 may be formed by etching the interlayer dielectric layer 60 and the contact-hole-etch-stop layer 50.
Further, as shown in FIG. 3, the metal oxide layer (not shown) on the top of the metal gate 22 may be removed by an argon sputter process. Because a metal silicide layer (not shown) may be formed on the drain region 40; and the metal silicide layer may protect the drain region 40 during the argon ion sputter process. Therefore, after removing the metal oxide layer by the argon sputter process, a portion of the semiconductors substrate 10 at the bottom of the HKMG structure 20 may be removed, and a depression 11 may be formed.
Further, as shown in FIG. 4, a second contact hole 80 may be formed by etching the interlayer dielectric layer 60 and the contact-hole-etch-stop layer 50.
Further, as shown in FIG. 5, a first conductive via 75 and a second conductive via 85 may be formed in the first contact hole 70 and the second contact hole 80, respectively, by filling the first hole 70 and the second hole 80 with a metal material. The first conductive via 75 is a shared via shared by the metal gate 22 and the drain region 40.
Referring to FIGS. 4-5, because the first conductive via 75 may penetrate into the semiconductor substrate 10 because of the existing of the depression 11, the distance between the source region 30 and the drain region 40 may be reduced, and it may be easy to generate a leakage current. Thus, the MOS transistor formed by the existing method may have a relatively large leakage current. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.